1. Field of the Invention
The present invention relates to a solid-state imaging device and a solid-state imaging apparatus. More particularly, it relates to a solid-state imaging device and a solid-state imaging apparatus capable of realizing a high frame rate.
2. Description of Related Art
In a video camera and a digital still camera, a CCD type solid-state imaging device using CCD registers in a charge transfer part has been used (refer to Japanese Unexamined Patent Application Publication NO. 2004-96546).
This CCD type solid-state imaging device has a plurality of pixels with photoelectric conversion elements (photodiodes: PD) two-dimensionally disposed in a matrix shape in an imaging area of a semiconductor substrate. Light incident upon each pixel is photoelectrically converted by the photodiode to generate electric charges, the electric charges are transferred to a floating diffusion (FD) region of an output part via a vertical transfer register and a horizontal transfer portion, a potential change in the FD region is detected by a MOS transistor, and this potential change is converted into an electric signal which is amplified and outputted as a video signal.
FIG. 5A is a schematic plan view showing a known CCD type solid-state imaging device, and FIG. 5B is a schematic cross sectional view taken along line A-A′ in FIG. 5A. This CCD type solid-state imaging device 101 is mainly constituted of an image area 102, a horizontal transfer portion 103 and an output part 104. The image area is constituted of light receiving portions (not shown) disposed in a matrix shape and a vertical transfer register (not shown) disposed in each vertical column of the respective light receiving portions to transfer charges from the respective light receiving portions. A light shielding film 105 is formed above the image area and the horizontal transfer portion.
The CCD type solid-state imaging device is formed on an n-type semiconductor substrate (N-sub) having a P-well region. A single ground potential supply source (GND) applies a ground potential to: a P-well region corresponding to the image area (the P-well region corresponding to the image area is hereinafter called an “image area P-well region”); a P-well region corresponding to the horizontal transfer portion (the P-well region corresponding to the horizontal transfer portion is hereinafter called a “horizontal transfer portion P-well region”); a P-well region corresponding to the output part (the P-well region corresponding to the output part is hereinafter called an “output part P-well region”); and the light shielding film. An N-well region is formed in an area corresponding to a pad 107 for applying a horizontal transfer clock.
In the CCD type solid-state imaging device constructed as above, electric charges read from the light receiving portions to the vertical transfer registers are transferred in a vertical direction, upon application of vertical transfer clocks from a timing signal generator circuit (not shown) to the vertical transfer registers. Electric charges transferred to the horizontal transfer portion are transferred in a horizontal direction, upon application of horizontal transfer clocks from the timing signal generator circuit to the horizontal transfer portion. The electric charges from the horizontal transfer portion are converted into a voltage in the FD region, and this voltage is read from the output part as an optical reception signal.
Because of recent market need for high image quality, the trend towards larger numbers of pixels in a CCD type solid-state imaging device has accelerated. There has also been a growing need for capturing a large number of images at the same time in a short time. It is therefore desired to realize a CCD type solid-state imaging device having a large number of pixels and a frame rate about the same degree as currently used frame rate.
A method of realizing a CCD type solid-state imaging device having a large number of pixels and a frame rate about the same degree as currently used frame rate may be (1) a method of raising a drive frequency for driving a CCD type solid imaging device and (2) a method of performing vertical transfer during an effective pixel period.
However, if a frame rate about the same degree as currently used frame rate is realized by raising a drive frequency for driving a CCD type solid-state imaging device, there may lead to problems such as an increase in a heat generation due to raising the drive frequency, an increase in a consumption power, an expensive substrate of the CCD type solid-state imaging device, an increase in the number of peripheral components. The realization of the frame rate about the same degree as currently used frame rate by raising a drive frequency for driving a CCD type solid imaging device, is hardly a satisfactory method. Furthermore, adopting only the countermeasure of raising a drive frequency is near at a limit relative to recent need for improvement on a frame rate.
If a frame rate about the same degree as currently used frame rate is realized by performing vertical transfer during an effective pixel period, there is a possibility of generation of crosstalk noises as indicated in the following [1] to [5].    [1]
As shown in FIG. 6, crosstalk noises are generated in the image area at the rise and fall of a vertical transfer clock during vertical transfer in the effective pixel period, and propagated to the image area P-well region via the light shielding film in the image area. The crosstalk noise propagated to the image area P-well region is propagated to the output part P-well region. Crosstalk noises are therefore generated in an output signal of the CCD type solid-state imaging device, due to the back gate effects.    [2]
As shown in FIG. 7, crosstalk noises are generated in the image area at the rise and fall of a vertical transfer clock during vertical transfer in the effective pixel period, and propagated to channel stop regions of the light receiving parts and the image area P-well region. The crosstalk noises propagated to the image area P-well region are propagated to the output part P-well region. Crosstalk noises are therefore generated in an output signal of the CCD type solid-state imaging device due to the back gate effects.    [3]
As shown in FIG. 8, crosstalk noises are generated in the image area at the rise and fall of a vertical transfer clock during vertical transfer in the effective pixel period, and propagated to the n-type semiconductor substrate via channel stop regions of the light receiving portions and the image area P-well region. The crosstalk noises propagated to the image area P-well region are propagated to the output part P-well region. Crosstalk noises are therefore generated in an output signal of the CCD type solid-state imaging device due to the back gate effects. The back gate effects from the n-type semiconductor substrate are large because of depletion of a P-well region (region indicated by character X in FIG. 8) just under an n-channel of a MOS transistor in the FD region and on the drive side of a first stage source follower of an output circuit.    [4]
As shown in FIG. 9, crosstalk noises are generated in the image area at the rise and fall of a vertical transfer clock during vertical transfer in the effective pixel period, and propagated to the n-type semiconductor substrate via channel stop regions of the light receiving portions and the image area P-well region, and to output signal wirings and an output signal pad 106. The crosstalk noises are therefore generated in an output signal of the CCD type solid-state imaging device.    [5]
As shown in FIG. 10A, high frequency components (high frequency noises) of the horizontal transfer clock are superposed upon the vertical transfer clock as coupling noises during vertical transfer in the effective pixel period.
The coupling noises superposed upon the vertical transfer clock are propagated to the P-well region so that high frequency noises are superposed upon an output signal of the CCD type solid-state imaging device. As shown in FIG. 10B, high frequency noises have different waveforms between the ordinary state and transition state of the vertical transfer clock. Therefore, when an output signal level of an arbitrary line of an image frame is observed, a fluctuation of the output signal arises as shown in FIG. 10C.
Techniques of realizing a high frame rate by shortening greatly a horizontal blanking period have been proposed in Japanese Unexamined Patent Application Publication No. 2005-269060. According to the techniques, vertical transfer is performed during the effective pixel period, and a drive clock waveform is supplied to the vertical transfer registers of a CCD type solid-state imaging device during vertical transfer. The drive clock waveform has rise and fall slopes having a transient speed ΔV/ΔT (where ΔV is a voltage and ΔT is a time) which allows a correlation double sampling circuit to eliminate crosstalk noises generated at the rise and fall of the drive clock waveform.
However, even by such techniques, crosstalk noises are not eliminated completely.